Last updated: 20 June 2009
Please send comments or questions to:
godfrey@isl.stanford.edu.
We conduct research in
Information and Computational Systems. Our
objective is to create
computational artifacts which satisfy optimality criteria as embedded
systems. This objective is enabled by constructive mathematical
engineering and, typically, by the availability of VLSI technology. The term
constructive
mathematical engineering is meant to encompass the theoretical
developments in information theory (including signal processing, and
various related special topics such as data compression, image analysis,
etc.) which lead to optimal solutions for information processing
systems. Due to the high computational performance and low cost of VLSI
circuits these solutions can be constructed in a cost-effective manner.
Specifically, we believe that VLSI
technology permits computation to be an integral part of most
engineering artifacts. This frees us from the constraints of the
performance of conventional electromechanical systems and permits the
construction of systems whose performance is determined by the results
of computation. This methodology allows us to construct systems that
directly implement theoretical results. In a broad sense, it is our
intent to close the long-standing gap between theory and engineering
practice, specifically through the use of VLSI computational constructs.
This will become a pervasive
methodology because systems which make use of active engineering
mathematics in the form of VLSI circuits will be very much more
cost-effective than conventional systems. Ultimately, this form of
engineering will provide cost-effective solutions to the most
challenging problems in information engineering: problems that we cannot
even begin to solve today.
Examples of results of this program are:
Imaging systems based on signal processing and A/D conversion at the pixel level. This work is reported by Boyd Fowler in his thesis, "CMOS Area Image Sensors with Pixel Level A/D Conversion."
Low-noise CMOS imaging circuits.
These have been developed by Boyd Fowler and the technical team
(Janusz Balicki, Steve Mims, Dana How, Michael D. Godfrey, and John Canfield) at
Pixel Devices (acquired by Agilent Technologies, who subsequently licensed
the technology
to Fairchild Imaging, Inc.) This technology is in use in imaging
products at
Fairchild Imaging, Inc.
Some of the techniques have been
presented in "Low Noise Readout using
Active Reset for CMOS APS," Boyd A. Fowler, Michael D. Godfrey, Janusz Balicki,
and John Canfield, Proc. SPIE Vol. 3965, p. 126-135, May 2000,
"Low FPN High Gain Capacitive
Transimpedance Amplifier for Low Noise CMOS Image Sensors," Boyd A. Fowler,
Janusz Balicki, Dana How, and Michael D. Godfrey, Proc. SPIE Vol. 4306, p. 68-77,
May 2001,
and "An Ultra Low Noise High Speed CMOS
Linescan Sensor
for Scientific and Industrial Applications," Boyd Fowler, Janusz Balicki,
Dana How, Steve Mims, John Canfield, and Michael D. Godfrey, Proc. SPIE, Electronic
Imaging Science and Technology, Jan. 2004, San Jose, CA. The
presentation slides for the
SPIE 2004 paper are also available.
This work has been further developed as described in
"Reset Noise Reduction in
Capacitive Sensors,"
Boyd Fowler, Michael D. Godfrey, and Steve Mims, IEEE TCAS-1, vol.53, No. 8,
August 2006.
The abstract from this paper reads:
Reset noise sets a fundamental detection limit on capacitive sensors. Many sensing circuits depend on accumulating charge on a capacitor as the sensing method. Reset noise is the noise that occurs when the capacitor is reset prior to the charge accumulation cycle. Therefore, it is important to understand the factors which determine reset noise, and how this noise may be mitigated. The purpose of this paper is to show how capacitive reset noise can be reduced during the reset cycle. We present and analyze three circuits that implement the basic methods for directly reducing capacitive reset noise. In addition, we present a time-domain technique for analyzing the time-varying statistics of these circuits. This technique makes use of Ito calculus to obtain solutions to the time-varying stochastic differential equations. Theoretical noise calculations and Monte Carlo simulation results are presented for each technique. We show that theory and simulation yield similar results.
Finally, we show in the examples that reset noise may be reduced by a factor of 20 or more. We also refer to implemented sensor arrays which achieve these results.
An analog VLSI model of the cochlear mechanism.
An analog wavelet transform chip.
The origins of this work were available on the web page of the Physics of Computation Group at Caltech, but this page is no longer active. If you are interested, take a look at other places where these ideas have been pursued, such as John Lazzaro's page where you will find the Chipmunk analog and digital VLSI design tools. Tobi Delbruck organized the Caltech Physics of Computation home page, which contained much interesting material. Tobi is now at INI in Zurich, and Carver Mead retired from Caltech in 2001. A good place to find out more these days is the Institute for Neuroinformatics at ETH/University of Zurich.
Or, if you are interested in other work that I have been involved in, such as statistics, mathematical economics, or computing look at other research.
As time permits I will add more material to this page, and provide more links to reports and publications.